During the manufacture and assembly of integrated circuits, the packaging process is one of the most critical steps. In fact, the cost of packaging an integrated circuit package can easily exceed the cost of manufacturing the integrated circuit chip. The increase in cost is due to the fact that the majority of device failures are generally packaging oriented. Therefore, there is a need for improved methods for packaging integrated circuits that reduce the cost of manufacturing and increase the reliability of the device.
A key step in integrated circuit fabrication is packaging the silicon chip in a manner that protects it in subsequent manufacturing steps and from the environment of its intended application. A critical step in the packaging process involves the inter-connection between the integrated circuit silicon chip and the board or substrate to which it is connected.
The packaging of an integrated circuit generally involves attaching an individual chip to a lead frame where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. Additionally, due to the increased miniaturization of integrated circuits, there has been a need to reduce both the size of the inter-connects between the silicon chip and the substrate, and also of the routing lines on the substrate. Concomitantly with the routing lines, the creation of vias within the substrate requires increased miniaturization.
U.S. Letters Pat. No. 5,561,594 (SGS-Thomson Microelectronics, Ltd.) discloses an electrical assembly in which the electrical component is mounted on a multi-layer printed circuit board having a plurality of conducting pins located in perforations within the board. The conducting pins located in the board have pointed ends that project above the board and make electric contact with solder bumps on the electrical component. While this specification describes an apparatus and method for flip-chip packaging, it does not address the need for smaller vias for use with high performance semi-conductor products. Furthermore, it uses conventional methods to create a printed circuit board. As with conventional manufacturing, the printed circuit board has standard size vias that are drilled through for each individual substrate increasing processing time.
U.S. Pat. No. 5,621,193 (Northrop Grumman Corp.) discloses a method for electrically connecting surface conductors to edge conductors by use of an intersecting side non-conductor substrate having a through hole in the substrate and metalization of the through hole. The electrical connections between the surface and the side include forming an intersecting ceiling plug in the via prior to cutting the intersecting side. The wraparound conduits as described, however, are vulnerable to damage during subsequent handling of the semi-conductor. Furthermore, the specification does not address the need to improve integrated circuit packaging.
Thus, it has been recognized herein that a need has arisen for a simple, effective apparatus and method for providing a substrate for interconnecting integrated circuits using fine pitch ball grid array (BGA) technology. The need has also arisen for a more versatile package for medium to high performance semi-conductors, and for substrates and methods of manufacturing substrates with increased efficiency and decreased cost. Furthermore, a need has arisen for a substrate that can be made using present equipment and using standard manufacturing techniques, but which decreases the number of drilling and cutting steps involved in the formation of via interconnects in substrates.